1. Field of the Invention
This invention relates generally to a data processing system, and more particularly to a data input control system for providing a processor with control data from a control storage.
2. Description of the Prior Art
Processors integrated on a one-chip semiconductor are adapted for use in various fields. There are two kinds of conventional data processing systems including such processors. In the first one, shown in FIG. 1A, a processor 2 includes a control storage (ROM) 1 therein. This type of processor does not necessarily have the flexibility of a program control system and, thus, it is only applicable to restricted fields because of the relatively small capacity and unchangeability of the control storage.
The second type of system, shown in FIG. 1B, comprises a processor 3 and a control storage (ROM) 4 located outside the processor 3 and connected therewith through ROM address lines 5 and ROM data lines 6, wherein the processor 3 and the control storage 4 are respectively integrated on one-chip semiconductor devices. However, it is unavoidable that a large number of terminals of the processor 3 are required for connecting with the ROM address and data lines 5 and 6.
If the number of the ROM address lines 5, which depends on the memory space of the control stage 4, is 11, for example, and that of the ROM data lines 6, which depends on read-out data lengths of the control storage 4, is 16, then the total number of the terminals used for them will be 27 in spite of the fact that only 42 terminals (pins), for example, are provided on one-chip semiconductor devices for conventional processors of this type. Therefore, the number of terminals that can be used for data processing purposes, other than the ROM address and data lines 5 and 6, are substantially reduced, resulting in functional deteriorations of the data processing system.
It may be considered that the number of the terminals on the processor 3 could be increased in order to overcome such functional deteriorations, but this leads to a large chip size for the processor 3 and does not meet required standards or functions thereof.